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| 2M x 8 - Bit Dynamic RAM 2k Refresh (Fast Page Mode) Advanced Information * 2 097 152 words by 8-bit organization * 0 to 70 C operating temperature * Fast Page Mode operation * Performance: -50 -60 60 15 30 104 40 ns ns ns ns ns HYB 5117800/BSJ-50/-60 HYB 3117800BSJ-50/-60 tRAC tCAC tAA tRC tPC RAS access time CAS access time Access time from address Read/Write cycle time Fast page mode cycle time 50 13 25 84 35 * Power dissipation: HYB5117800 -50 Power Supply Active TTL Standby CMOS Standby 440 -60 5 10% 385 11 5.5 HYB3117800 -50 288 -60 3.3 0.3 V 252 7.2 3.6 mW mW mW * Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh and test mode * All inputs, outputs and clocks fully TTL (5 V versions) and LV-TTL (3.3 V version)-compatible * 2048 refresh cycles / 32 ms (2k-refresh) * Plastic Package: P-SOJ-28-3 400 mil Semiconductor Group 1 1998-10-01 HYB 5(3)117800/BSJ-50/-60 2M x 8 DRAM The HYB 5(3)117800 are 16 MBit dynamic RAMs based on the die revisions "G" & "F" and organized as 2 097 152 words by 8-bits. The HYB 5(3)117800 utilizes a submicron CMOS silicon gate process technology, as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. Multiplexed address inputs permit the HYB 5(3)117800 to be packaged in a standard SOJ-28 plastic package. Package with 400 mil width are available. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. Ordering Information Type HYB 5117800BSJ-50 HYB 5117800BSJ-60 HYB 3117800BSJ-50 HYB 3117800BSJ-60 Ordering Code Q67100-Q1092 Q67100-Q1093 on request on request Package Descriptions P-SOJ-28-3 400 mil 5 V 50 ns FPM-DRAM P-SOJ-28-3 400 mil 5 V 60 ns FPM-DRAM P-SOJ-28-3 400 mil 3.3 V 50 ns FPM-DRAM P-SOJ-28-3 400 mil 3.3 V 60 ns FPM-DRAM P-SOJ-28 400 mil V CC I/O1 I/O2 I/O3 I/O4 WE RAS N.C. A10 A0 A1 A2 A3 V CC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 V SS 27 I/O8 26 I/O7 25 I/O6 24 I/O5 23 CAS 22 OE 21 A9 20 A8 19 A7 18 A6 17 A5 16 A4 15 V SS SPP02803 Pin Names and Configuration A0 - A10 A0 - A9 RAS OE I/O1 - I/O8 CAS WE Row Address Inputs Column Address Inputs Row Address Strobe Output Enable Data Input/Output Column Address Strobe Read/Write Input Power Supply + 5 V for HYB 5117800 + 3.3 V for HYB 3117800 Ground (0 V) Not Connected VCC VSS N.C. Semiconductor Group 2 1998-10-01 HYB 5(3)117800/BSJ-50/-60 2M x 8 DRAM I/O1 I/O2 I/O8 Data IN Buffer WE CAS 8 No.2 Clock Generator & Data OUT Buffer OE 8 10 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 Column Address Buffers (10) 10 Column Decoder Refresh Controller Sense Amplifier I/O Gating 4 Refresh Counter (11) 11 11 Row Address Buffers (11) 11 Row Decoder 2048 1024 x8 Memory Array 2048 x 1024 x 8 RAS No.1 Clock Generator Voltage Down Generator SPB03456 VCC VCC (internal) Block Diagram Semiconductor Group 3 1998-10-01 HYB 5(3)117800/BSJ-50/-60 2M x 8 DRAM Absolute Maximum Ratings Operating temperature range ........................................................................................... 0 to 70 C Storage temperature range........................................................................................ - 55 to 150 C Input/output voltage (5 V versions) ................................................... - 0.5 to min (VCC + 0.5, 7.0) V Input/output voltage (3.3 V versions) ................................................ - 0.5 to min (VCC + 0.5, 4.6) V Power supply voltage (5 V versions) ....................................................................... - 1.0 V to 7.0 V Power supply voltage (3.3 V versions) .................................................................... - 1.0 V to 4.6 V Power dissipation (5 V versions) ............................................................................................. 1.0 W Power dissipation (3.3 V versions) .......................................................................................... 0.5 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = 0 to 70 C, VSS = 0 V, tT = 2 ns Parameter 5 V Versions Power supply voltage Input high voltage Input low voltage Output high voltage (IOUT = - 5 mA) Output low voltage (IOUT = 4.2 mA) 3.3 V Versions Power supply voltage Input high voltage Input low voltage TTL Output high voltage (IOUT = - 2 mA) TTL Output low voltage (IOUT = 2 mA) CMOS Output high voltage (IOUT = - 100 A) CMOS Output low voltage (IOUT = 100 A) Symbol Limit Values min. max. 5.5 0.8 - 0.4 3.6 0.8 - 0.4 0.2 Unit Test Condition VCC VIH VIL VOH VOL VCC VIH VIL VOH VOL VOH VOL 4.5 2.4 - 0.5 2.4 - 3.0 2.0 - 0.5 2.4 - - V 1 1 1 1 VCC + 0.5 V V V V V VCC + 0.5 V V V V V V 1 1 1 1 VCC - 0.2 - Semiconductor Group 4 1998-10-01 HYB 5(3)117800/BSJ-50/-60 2M x 8 DRAM DC Characteristics (cont'd) TA = 0 to 70 C, VSS = 0 V, tT = 2 ns Parameter Common Parameters Input leakage current (0 V VIH VCC + 0.3 V, all other pins = 0 V) Output leakage current (DO is disabled, 0 V VOUT VCC + 0.3 V) Average VCC supply current -50 ns version -60 ns version (RAS, CAS, address cycling: tRC = tRC MIN.) Standby VCC supply current (RAS = CAS = VIH) ICC2 Average VCC supply current, during RAS-only ICC3 refresh cycles -50 ns version -60 ns version (RAS cycling, CAS = VIH, tRC = tRC MIN.) Average VCC supply current, during fast page mode Symbol Limit Values min. max. 10 10 Unit Test Condition II(L) IO(L) ICC1 - 10 - 10 A A 1 1 - - - - - 80 70 2 80 70 mA mA mA mA mA 2, 3, 4 2, 3, 4 - 2, 4 2, 4 ICC4 - - 25 20 1 mA mA mA -50 ns version -60 ns version (RAS = VIL, CAS, address cycling: tPC = tPC MIN.) 2, 3,) 4 2, 3, 4 Standby VCC supply current (RAS = CAS = VCC - 0.2 V) ICC5 - 1 Average VCC supply current, during CASICC6 before-RAS refresh mode -50 ns version -60 ns version (RAS, CAS cycling: tRC = tRC MIN.) Capacitance TA = 0 to 70 C,VCC = 5 V 10 %, f = 1 MHz Parameter Input capacitance (A0 to A10) Input capacitance (RAS, CAS, WE, OE) I/O capacitance (I/O1 to I/O8) - - 80 70 mA mA 2, 4 2,) 4 Symbol Limit Values min. max. 5 7 7 - - - Unit pF pF pF CI1 CI2 CIO Semiconductor Group 5 1998-10-01 HYB 5(3)117800/BSJ-50/-60 2M x 8 DRAM AC Characteristics 5, 6 TA = 0 to 70 C, VCC = 5 V 10 % / VCC = 3.3 V 0.3 V, tT = 5 ns Parameter Symbol min. Common Parameters Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period Read Cycle Access time from RAS Access time from CAS Access time from column address OE access time Column address to RAS lead time Read command setup time Read command hold time Read command hold time referenced to RAS CAS to output in low-Z Output buffer turn-off delay Output buffer turn-off delay from OE Limit Values -50 max. min. -60 max. Unit Note tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tT tREF 90 30 50 13 0 8 0 10 18 13 13 50 5 3 - - - 10k 10k - - - - 37 25 110 40 60 15 0 10 0 15 20 15 15 60 - - 10k 10k - - - - 45 30 - - - 50 32 ns ns ns ns ns ns ns ns ns ns ns ns ns ms 7 - 50 32 5 3 - tRAC tCAC tAA tOEA tRAL tRCS tRCH tRRH tCLZ tOFF tOEZ 6 - - - - 25 0 0 0 0 0 0 50 13 25 13 - - - - - 13 13 - - - - 30 0 0 0 0 0 0 60 15 30 15 - - - - - 15 15 ns ns ns ns ns ns ns ns ns ns ns 8, 9 8, 9 8, 10 11 11 8 12 12 Semiconductor Group 1998-10-01 HYB 5(3)117800/BSJ-50/-60 2M x 8 DRAM AC Characteristics (cont'd) 5, 6 TA = 0 to 70 C, VCC = 5 V 10 % / VCC = 3.3 V 0.3 V, tT = 5 ns Parameter Symbol min. Data to OE low delay CAS high to data delay OE high to data delay Write Cycle Write command hold time Write command pulse width Write command setup time Write command to RAS lead time Write command to CAS lead time Data setup time Data hold time Data to CAS low delay Read-Modify-Write Cycle Read-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE command hold time Fast Page Mode Cycle Fast page mode cycle time CAS precharge time Access time from CAS precharge RAS pulse width CAS precharge to RAS Delay Limit Values -50 max. min. - - - 0 15 15 -60 max. - - - ns ns ns 13 14 14 Unit Note tDZO tCDD tODD 0 13 13 tWCH tWP tWCS tRWL tCWL tDS tDH tDZC 8 8 0 13 13 0 10 0 - - - - - - - - 10 10 0 15 15 0 10 0 - - - - - - - - ns ns ns ns ns ns ns ns 16 16 13 15 tRWC tRWD tCWD tAWD tOEH 126 68 31 43 13 - - - - - 150 80 35 50 15 - - - - - ns ns ns ns ns 15 15 15 tPC tCP tCPA tRAS tRHPC 35 10 - 50 30 - - 30 200k - 40 10 - 60 35 - - 35 200k - ns ns ns ns ns 7 Semiconductor Group 7 1998-10-01 HYB 5(3)117800/BSJ-50/-60 2M x 8 DRAM AC Characteristics (cont'd) 5, 6 TA = 0 to 70 C, VCC = 5 V 10 % / VCC = 3.3 V 0.3 V, tT = 5 ns Parameter Symbol min. Fast Page Mode Read-Modify-Write Cycle Fast page mode read-write cycle time CAS precharge to WE CAS-before-RAS Refresh Cycle CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time Write hold time referenced to RAS CAS-before-RAS Counter Test Cycle CAS precharge time Test Mode CAS hold time Write command setup time Write command hold time RAS hold time in test mode Limit Values -50 max. min. -60 max. Unit Note tPRWC tCPWD 71 48 - - 80 55 - - ns ns tCSR tCHR tRPC tWRP tWRH 10 10 5 10 10 - - - - - 10 10 5 10 10 - - - - - ns ns ns ns ns tCPT 35 - 40 - ns tCHRT tWTS tWTH tRAHT 30 10 10 30 - - - - 30 10 10 30 - - - - ns ns ns ns Semiconductor Group 8 1998-10-01 HYB 5(3)117800/BSJ-50/-60 2M x 8 DRAM Notes All voltages are referenced to VSS. ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less during a fast page mode cycle (tPC). 5. An initial pause of 200 s is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6. AC measurements assume tT = 5 ns. 7. VIH (MIN.) and VIL (MAX.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8. Measured with a load equivalent to 2 TTL loads and 100 pF. 9. Operation within the tRCD (MAX.) limit ensures that tRAC (MAX.) can be met. tRCD (MAX.) is specified as a reference point only: If tRCD is greater than the specified tRCD (MAX.) limit, then access time is controlled by tCAC. 10.Operation within the tRAD (MAX.) limit ensures that tRAC (MAX.) can be met. tRAD (MAX.) is specified as a reference point only: If tRAD is greater than the specified tRAD (MAX.) limit, then access time is controlled by tAA. 11.Either tRCH or tRRH must be satisfied for a read cycle. 12.tOFF (MAX.) and tOEZ (MAX.) define the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. 13.Either tDZC or tDZO must be satisfied. 14.Either tCDD or tODD must be satisfied. 15.tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (MIN.), the cycle is an early write cycle and the I/O pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (MIN.), tCWD > tCWD (MIN.), tAWD > tAWD (MIN.) and tCPWD > tCPWD (MIN.) , the cycle is a read-write cycle and I/O pins will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate. 16.These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles. 1. 2. 3. 4. Semiconductor Group 9 1998-10-01 HYB 5(3)117800/BSJ-50/-60 2M x 8 DRAM t RC t RAS VIH RAS t RP VIL t CSH t RCD VIH CAS t RSH t CAS t CRP VIL t RAD t ASR VIH Address Row Column Row t RAL t CAH t ASR t ASC VIL t RAH t RCS t RRH t AA t OEA t RCH VIH WE VIL VIH OE VIL t DZC t DZO t ODD t CDD I/O (Inputs) VIH VIL t CAC t CLZ t OEZ Valid Data OUT Hi Z t OFF I/O (Outputs) V OL VOH Hi Z t RAC "H" or "L" SPT03025 Read Cycle Semiconductor Group 10 1998-10-01 HYB 5(3)117800/BSJ-50/-60 2M x 8 DRAM t RC t RAS VIH RAS t RP VIL t CSH t RCD VIH CAS t RSH t CAS t RAL t CAH t CRP VIL t RAD t ASR VIH Address Row Column Row t ASC t ASR VIL t RAH t WCS t CWL t WP t WCH t RWL VIH WE VIL VIH OE VIL t DS I/O (Inputs) t DH VIH Valid Data IN VIL Hi Z VOH I/O (Outputs) V OL "H" or "L" SPT03026 Write Cycle (Early Write) Semiconductor Group 11 1998-10-01 HYB 5(3)117800/BSJ-50/-60 2M x 8 DRAM t RC t RAS VIH RAS t RP VIL t CSH t RCD VIH CAS t RSH t CAS t RAL t CAH t CRP VIL t RAD t ASR VIH Address Row Column Row t ASC t ASR VIL t RAH t CWL t RWL t WP VIH WE VIL t OEH VIH OE VIL t DZO t DZC I/O (Inputs) t ODD t DS t DH VIH Valid Data VIL t CLZ t OEA t OEZ VOH I/O (Outputs) V OL Hi Z Hi Z "H" or "L" SPT03027 Write Cycle (OE Controlled Write) Semiconductor Group 12 1998-10-01 HYB 5(3)117800/BSJ-50/-60 2M x 8 DRAM t RWC t RAS VIH RAS VIL t CSH t RSH t RCD VIH CAS t RP t CAS t CRP VIL t ASR VIH Address Row t RAH t ASC Column t CAH t ASR Row VIL t RAD t AWD t CWD t RWD VIH WE t CWL t RWL t WP VIL t RCS t AA t OEA t OEH VIH OE VIL t DZC t DZO t DS t DH Valid Data IN I/O (Inputs) VIH VIL t CAC t CLZ t ODD t OEZ Data OUT VOH I/O (Outputs) V OL t RAC "H" or "L" SPT03028 Read-Write (Read-Modify-Write) Cycle Semiconductor Group 13 1998-10-01 HYB 5(3)117800/BSJ-50/-60 2M x 8 DRAM t RASP VIH RAS VIL t PC t RCD VIH CAS t RHCP t CAS t CP t RSH t CAS t RP t CRP t CAS VIL t RAH t ASR VIH Address Row Column Column Column Row t ASC t CSH t CAH t ASC t CAH t ASC t CAH t ASR VIL t RAD t RCS VIH WE t RCH t RCS t RCS t RRH t RCH VIL t AA t OEA VIH OE t CPA t AA t OEA t CPA t AA t OEA VIL t DZC t DZO t DZC t DZO t ODD t DZC t DZO t ODD t ODD t CDD I/O (Inputs) VIH VIL t OFF t OEZ t RAC t CAC t CLZ t CAC t CLZ Valid Data OUT "H" or "L" SPT03029 t OFF t OEZ t CAC t CLZ Valid Data OUT t OFF t OEZ VOH I/O (Outputs) V OL Valid Data OUT Fast Page Mode Read Cycle Semiconductor Group 14 1998-10-01 HYB 5(3)117800/BSJ-50/-60 2M x 8 DRAM t RASP VIH RAS VIL t PC t CAS t RCD VIH CAS t RP t CAS t CP t RSH t CAS t CRP VIL t RAH t ASR VIH Address Row Column Column Column Row t RAL t CAH t ASC t CAH t ASC t CAH t ASR t ASC VIL t RAD t WCS t CWL t WCH t WP VIH WE t WCS t CWL t WCH t WP t WCS t RWL t CWL t WCH t WP VIL VIH OE VIL t DS I/O (Inputs) t DH Valid Data IN t DS t DH Valid Data IN Hi Z t DS t DH Valid Data IN VIH VIL VOH I/O (Outputs) V OL "H" or "L" SPT03030 Fast Page Mode Early Write Cycle Semiconductor Group 15 1998-10-01 HYB 5(3)117800/BSJ-50/-60 2M x 8 DRAM t RAS VIH RAS VIL t CSH t RP t CP t RCD VIH CAS t PRWC t CAS t CAS t RSH t CRP t CAS VIL t ASR VIH Address Row Column Column Column Row t RAD t RAH t ASC t CAH t CAH t ASC t ASC t RAL t CAH t ASR VIL t RWD t CWD t RCS VIH WE t CWL t CPWD t CWD t CWL t CPWD t CWD t RWL t CWL VIL t AA t AWD t OEA t OEH t WP t AWD t OEA t OEH t WP t AWD t OEA t WP t OEH VIH OE VIL t DZC t DZO VIH I/O (Inputs) V IL t CAC t RAC VOH I/O (Outputs) V OL t CLZ t CLZ t ODD t DZC Data IN t CLZ t CPA t CPA t ODD Data IN t DZC t ODD Data IN t DH t DS t OEZ Data OUT t DH t AA t DS t OEZ Data OUT t CAC t AA t OEZ Data OUT t DH t DS "H" or "L" SPT03031 Fast Page Mode Late Write and Read-Modify Write Cycle Semiconductor Group 16 1998-10-01 HYB 5(3)117800/BSJ-50/-60 2M x 8 DRAM t RC t RAS VIH RAS t RP VIL t CRP t RPC VIH CAS VIL VIH Address t ASR t RAH t ASR Row Row VIL VOH I/O (Outputs) V OL Hi Z "H" or "L" SPT03032 RAS-only Refresh Cycle Semiconductor Group 17 1998-10-01 HYB 5(3)117800/BSJ-50/-60 2M x 8 DRAM t RC t RP VIH RAS t RAS t RP VIL t RPC t CP t CSR VIH CAS t CHR t RPC t CRP VIL t WRH t WRP VIH WE VIL VIH OE VIL t ODD I/O (Inputs) VIH VIL t CDD t OEZ I/O (Outputs) V OL VOH t OFF Hi Z "H" or "L" SPT03033 CAS-before-RAS Refresh Cycle Semiconductor Group 18 1998-10-01 HYB 5(3)117800/BSJ-50/-60 2M x 8 DRAM t RC t RP t RAS VIH RAS t RC t RP t RAS VIL t RCD VIH CAS t RSH t CHR t CRP VIL t RAD t ASC t RAH t ASR VIH Address Row Column Row t WRP t CAH t WRH t ASR VIL VIH WE t RCS t RRH VIL t AA t OEA VIH OE VIL t DZC t DZO t CDD t ODD I/O (Inputs) VIH VIL t CLZ t RAC t CAC t OEZ Valid Data OUT Hi Z t OFF VOH I/O (Outputs) V OL "H" or "L" SPT03034 Hidden Refresh Cycle (Read) Cycle Semiconductor Group 19 1998-10-01 HYB 5(3)117800/BSJ-50/-60 2M x 8 DRAM t RC t RAS VIH RAS t RC t RP t RAS t RP VIL t RCD VIH CAS t RSH t CHR t CRP VIL t RAD t ASC t RAH t ASR VIH Address Row Column Row t CAH t ASR VIL t WCS t WCH t WP t WRH t WRP VIH WE VIL t DS t DH I/O (Input) VIN Valid Data VIL Hi Z VOH I/O (Output) V OL "H" or "L" SPT03035 Hidden Refresh Early Write Cycle Semiconductor Group 20 1998-10-01 HYB 5(3)117800/BSJ-50/-60 2M x 8 DRAM Read Cycle VIH RAS t RAS t RP VIL t CHR t CSR VIH CAS t RSH t CP t CAS t RAL t CAH t ASC t ASR Row VIL VIH Address Column VIL VIH WE t WRP t AA t CAC t OEA t RRH VIL VIH OE t WRH t RCS t RCH VIL t DZC VIH I/O (Inputs) V IL t DZO t CLZ I/O (Outputs) V t CDD t ODD t OFF t OEZ Data OUT VOH OL t WCS t WRP t RWL t CWL t WCH t WRH t DH Write Cycle VIH WE VIL VIH OE VIL t DS I/O (Inputs) V IL VIH Data IN Hi Z VOH I/O (Outputs) V OL "H" or "L" SPT03036 CAS-before-RAS Refresh Counter Test Cycle Semiconductor Group 21 1998-10-01 HYB 5(3)117800/BSJ-50/-60 2M x 8 DRAM t RC t RP VIH RAS t RAS t RP VIL t RPC t CP t CSR VIH CAS t RPC t CHR t CRP VIL t RAH t ASR VIH Address Row VIL t WTH t WTS VIH WE VIL VIH OE VIL t ODD I/O (Inputs) VIH VIL Hi Z t CDD t OEZ I/O (Outputs) V OL VOH t OFF Hi Z "H" or "L" SPT03042 Test Mode Entry Semiconductor Group 22 1998-10-01 HYB 5(3)117800/BSJ-50/-60 2M x 8 DRAM Package Outlines Plastic Package P-SOJ-28-3 (400mil) (SMD) (Plastic small outline J-leaded) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 23 Dimensions in mm 1998-10-01 GPJ05699 |
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